AES/Rijndael: speed

Cross-table

Machine/ compiler Encryption Decryption Enc Key Expansion Dec Key Expansion Availability
CyclesSpeed (MBit/s) CyclesSpeed (Mbit/s) Cycles Cycles
64-bit AMD/Intel software
AMD Athlon 64 4000+ (2.4 GHz) /* Scaled based on results on 3000+)
gcc 4.10 199
Updated: 10.04.06
1472.2 1991472.2 127
Updated: 10.04.06
308
Updated: 10.04.06
[$] (Helger Lipmaa) --- same code as for P3
32-bit software
Pentium 4 (3.2 GHz)
assembly 254
Updated: 17.12.03
1537.9 2571519.9 158
Updated: 17.12.03
269
Updated: 17.12.03
[$] (Helger Lipmaa)
AMD Athlon (2.25 GHz)
gcc 3.0.2 319861.0 344798.4 155348 [$] (Helger Lipmaa)
Pentium III and III-M (1.33GHz)
assembly 226 Updated: 13.05.02718.4 Same as below (C)Same as below (C) [$] (Helger Lipmaa)
assembly 280579.8 280579.8 Free (Brian Gladman)
gcc 3.0.2 348466.5 376431.8 168280 [$] (Helger Lipmaa)
MVC+ 6.0 362448.5 362448.5 202306 Free (Brian Gladman)
Pentium (233 MHz)
assembly 32088.9 N/A (Antoon Bosselaers)
Gl, MVC+ 6.0 70240.5 Free (Brian Gladman)
EGCS 1.0.2 95029.9 Free
Alpha AXP 21164 (600 MHz)
C
439166.8 Weiss etc
gcc 490149.5 ? (Louis Granboulan)
DEC CC 516141.9 ? (Louis Granboulan)
gcc 281 617118.7 ? (Louis Granboulan)
Macintosh: PowerPC G4 (7400, 500 MHz)
ref 3.0 C code
(gcc 3.3 -O2, Denis Ahrens)
401
Updated: 17.12.03
159 407
Updated: 17.12.03
626
Added: 17.12.03
822
Added: 17.12.03
Macintosh: PowerPC 7457, 1.25 HHz
Added: 17.12.03
ref 3.0 C code
(gcc 3.3 -O2, Denis Ahrens)
385415 391409 288921
Alpha AXP 21264 (1 GHz)
Assembler 210 581.3 Weiss
(estimated)
C 293 416.6 Weiss etc
SPARC
SPARCv9 Sun C 6.0 (480 MHz) 270217.0 N/A (Helger Lipmaa)
IA-64 family
Merced asm 170
McKinley asm 142-
McKinley snapshot asm 124 Worley etc
IA-64++
Worley etc
124
Other (RISC, 680x0, ...)
PA-RISC 7000 735 Free
PA-RISC 8200 186
PA-RISC 8500
Worley etc
185
StrongARM 690 ? (sci.crypt posting by Eric Young)
ARM-based SmartCards 1467 ? (UCL/Crypto)
DSPs
TMS320C541, TI C 1.20 3518 Enigma SOI, Free
TMS320C6201 228 [?] Wollinger etc
8-bit processors
6805 14324 (GK) Free
68xx 8390 (68HC08)
MCS51, 8051 3168 (1016 bytes) ?
MCS51, 8051 3744 (826 bytes) ?
FPGA
Virtex E
cycles per block/MHz/CLB Slices/BlockRAMS
(enc-dec, incl key schedule)
//460/10700Free Weaver
Spartan II-100
cycles per block/MHz/CLB Slices/BlockRAMS
//460/10500FWeaver
Xilinx Virtex XCV 1000
cycles per block/MHz/CLB Slices
//2507414.2 Gaj, Chodowiec
Xilinx Virtex V800FG676-6
cycles per block/MHz/CLB Slices/Gate count
(encryption only, includes key schedule)
11/31.3/2272/101506 364.2Panu Hämäläinen, 2001 New, 02.01.04
Xilinx Virtex
slices per core w/o key setup
4312353.00 Dandalis, Prasanna, Rolim
Xilinx Virtex (slices per core) 2902331.5 Gaj etc
Xilinx Virtex XCV1000BG560-4 FPGA
cycles per block/MHz/CLB Slices
6/14.1/5302 300.1 Elbirt, Yip, Chetwynd, Paar
Spartan II-100 //800/10250FWeaver
Virtex E //800/10250FWeaver
Xilinx Virtex V800FG676-6
cycles per block/MHz/CLB Slices/Gate count
(encryption only, includes key schedule)
11/21.2/3267/114414 246.7Panu Hämäläinen, 2001 New, 02.01.04
Altera Flex10KE (slices per core) 1585232.7 Fischer
ASIC
Mitsubishi 0.35micron CMOS ASIC 1950.03Ichikawa etc
0.25micron ASIC
trans count
39,0001280Hi/fn
NSA (area um2, trans count)33851050; 641681605.77NSA Hardware Test
UCLA 0.18micron CMOS ASIC 1600UCLA homepage

Only iterative (feedback) modes are considered: i.e., modes where encryption of the previous block has to be finished before encryption of the next block can begin. (This excludes several FPGA and hardware implementations. See here for non-feedback modes.)

  1. The PA-RISC 8200 implementation is as communicated by Doug Whiting, but done by the HP folks.
  2. Merced/McKinley (the first and the second generation Intel IA64 processor) estimations are a courtesy of Doug Whiting.

Formula used to compute Mbit/s: mhz*1000*1000/1024/1024*128/cycles.


Maintained by Helger Lipmaa. Don't hesitate to email me if you have any corrections/additions/comments.

Valid HTML 4.01!